# The lang/verilator port

## verilator-5.044 – very fast free Verilog HDL simulator

## Description

    Verilator is the fastest free Verilog HDL simulator, and beats most
    commercial simulators. It compiles synthesizable Verilog (not test-bench
    code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
    or SystemC code. It is designed for large projects where fast simulation
    performance is of primary concern, and is especially well suited to
    generate executable models of CPUs for embedded software design teams.

WWW: https://www.veripool.org/wiki/verilator/Intro

Only for arches
  aarch64 aarch64 alpha alpha amd64 amd64 arm arm hppa hppa i386 i386 m88k mips64 mips64 mips64el mips64el powerpc powerpc powerpc64 powerpc64 riscv64 riscv64 sh sparc64 sparc64
Categories:
  devel lang

## Library dependencies

- STEM->=15,<16:lang/gcc/15,-libs

## Build dependencies

- STEM->=15,<16:lang/gcc/15
- STEM->=15,<16:lang/gcc/15,-c++
- devel/autoconf/2.72
- devel/bison
- devel/gmake
- devel/help2man
- devel/metaauto
- lang/python/3

## Run dependencies