L8( t'tsd,px30-ringneck-haikourockchip,px30 +07Theobroma Systems PX30-uQ7 SoM on Haikou devkitaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff390000/mmc@ff380000/i2c@ff190000/rtc@6f/i2c@ff180000/pmic@20/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZ  +cpu@1cpuarm,cortex-a35psciZ  +cpu@2cpuarm,cortex-a35psciZ  + cpu@3cpuarm,cortex-a35psciZ  + idle-states3pscicpu-sleeparm,idle-state@Qhxy+cluster-sleeparm,idle-state@Qhy+opp-table-0operating-points-v2+opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkin%psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal2HVh tripstrip-point-0xppassivetrip-point-1xLpassive+soc-critx8 criticalcooling-mapsmap0 gpu-thermal2dHh tripsgpu-thresholdxppassivegpu-targetxLpassive+gpu-critx8 criticalcooling-mapsmap0 xin24m fixed-clock%n6xin24m+fpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller++hpower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd++io-domains$rockchip,px30-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart %%baudclkapb_pclk"&&'txrx1;HdefaultV'okayi2s@ff060000rockchip,px30-i2s-tdm  mclk_txmclk_rxhclk"&&'txrx`(m ttx-mrx-mHdefaultV)*+,okay+i2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk"&&'txrxHdefaultV-./0 disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk"&&'txrxHdefaultV1234 disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   +syscon@ff140000$rockchip,px30-grfsysconsimple-mfd++(io-domains rockchip,px30-io-voltage-domainokay5655 57&5lvdsrockchip,px30-lvds:8?dphy`(Ilvds disabledports+port@0+endpoint@0Y9+endpoint@1Y:+port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk"&&'txrx1;Hdefault V;<= disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk"&&'txrx1;HdefaultV> disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk"&&'txrx1;Hdefault V?@A disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk"&& 'txrx1;Hdefault VBCD disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk1;HdefaultVEokay iF i2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk HdefaultVG+okaypmic@20rockchip,rk809  FVHHdefault%xin32ksIIII555IregulatorsDCDC_REG1vdd_log~)pAqVjregulator-state-mem|~DCDC_REG2vdd_arm~)pAqVj+regulator-state-mem~DCDC_REG3vcc_ddrVjregulator-state-mem|DCDC_REG4 vcc_3v0_1v8w@)-Vj+7regulator-state-mem|-DCDC_REG5vcc_3v32Z)2ZVj+5regulator-state-mem|2ZLDO_REG2vcc_1v8w@)w@Vj+eregulator-state-mem|w@LDO_REG3vcc_1v0B@)B@Vjregulator-state-mem|B@LDO_REG5 vccio_sdw@)2ZVj+6regulator-state-mem|2ZLDO_REG7VjB@)B@vcc_lcdregulator-state-memB@LDO_REG8 vcc_1v8_lcdw@)w@Vjregulator-state-mem|w@LDO_REG9 vcca_1v8w@)w@Vjregulator-state-memw@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk HdefaultVJ+okayfan@18 ti,amc6821rtc@6f isil,isl1208oi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  HdefaultVK+okaycodec@a fsl,sgtl5000 LMNO+i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  HdefaultVP+okayeeprom@50P atmel,24c01Nspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk"& & 'txrxHdefaultVQRST+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk"&&'txrxHdefaultVUVWXY+okay Z Z watchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkHdefaultV[okaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkHdefaultV\ disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkHdefaultV] disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkHdefaultV^ disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkHdefaultV_ disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkHdefaultV` disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkHdefaultVa disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkHdefaultVb disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ apb_pclk4+&tsadc@ff280000rockchip,px30-tsadc( $?,OP,Xtsadcapb_pclkm ttsadc-apb`(dHinitdefaultsleepVc{dcokay+ saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-Wsaradcapb_pclkm tsaradc-apbokayenvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphymtphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ f% xin24mgpll`(%8?@IOFq рр +clock-controller@ff2bc000rockchip,px30-pmucru+fxin24m`(%?%%% OG+%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy % phyclk%?g usb480m_phyokay+ghost-port D linestateokay+jotg-port$BA@otg-bvalidotg-idlinestateokay+iphy@ff2e0000rockchip,px30-dsi-dphy.% E refpclkm>tapbh  disabled+8phy@ff2f0000rockchip,px30-csi-dphy/@Fpclkh m/tapb`( disabled+usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otgotg/>@ :i ?usb2-phyhokayusb@ff340000 generic-ehci4 <:j?usbhokayusb@ff350000 generic-ohci5 =:j?usbhokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed`(MrmiiHdefaultVklh m^ tstmmacethokay VZf |PP5outputmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sampleрHdefaultVmnophokay6 #F,7Nmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sampleрHdefault Vqrsh  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sampleрHdefault Vtuvh okayCRw]757spi@ff3a0000 rockchip,sfc:@ 8:clk_sfchclk_sfc VxyzHdefaulth  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97ahbnfc?7OрHdefault V{|}~h  disabledopp-table-1operating-points-v2+opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIh okay+video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu aclkhclkkh iommu@ff442800rockchip,iommuD( Q aclkifacerh +dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KDpclk:8?dphyh m=tapb`(+ disabledports+port@0+endpoint@0Y+endpoint@1Y+port@1vop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vopm345 taxiahbdclkkh  disabledport++ endpoint@0Y+endpoint@1Y+9iommu@ff460f00rockchip,iommuF M aclkifaceh r disabled+vop@ff470000rockchip,px30-vop-litG Naclk_vopdclk_vophclk_vopm789 taxiahbdclkkh  disabledport++ endpoint@0Y+endpoint@1Y+:iommu@ff470f00rockchip,iommuG N aclkifaceh r disabled+isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_ispaclkhclkpclkk:?dphyh  disabledports+port@0+iommu@ff4a8000rockchip,iommuJ F aclkifaceh r+qos@ff518000rockchip,px30-qossysconQ +qos@ff520000rockchip,px30-qossysconR +$qos@ff52c000rockchip,px30-qossysconR +qos@ff538000rockchip,px30-qossysconS +qos@ff538080rockchip,px30-qossysconS +qos@ff538100rockchip,px30-qossysconS +qos@ff538180rockchip,px30-qossysconS +qos@ff540000rockchip,px30-qossysconT +qos@ff540080rockchip,px30-qossysconT +qos@ff548000rockchip,px30-qossysconT +qos@ff548080rockchip,px30-qossysconT + qos@ff548100rockchip,px30-qossysconT +!qos@ff548180rockchip,px30-qossysconT +"qos@ff548200rockchip,px30-qossysconT +#qos@ff550000rockchip,px30-qossysconU +qos@ff550080rockchip,px30-qossysconU +qos@ff550100rockchip,px30-qossysconU +qos@ff550180rockchip,px30-qossysconU +qos@ff558000rockchip,px30-qossysconU +qos@ff558080rockchip,px30-qossysconU +pinctrlrockchip,px30-pinctrl`(+gpio@ff040000rockchip,gpio-bank %+Fgpio@ff250000rockchip,gpio-bank% \+gpio@ff260000rockchip,gpio-bank& ]bios-disable-override-hogm bios_disable_overridebios-disable-n-hogm bios_disablegpio@ff270000rockchip,gpio-bank' ^+Zpcfg-pull-up+pcfg-pull-downpcfg-pull-none +pcfg-pull-none-2ma  pcfg-pull-up-2ma pcfg-pull-up-4ma +pcfg-pull-none-4ma  pcfg-pull-down-4ma pcfg-pull-none-8ma  +pcfg-pull-up-8ma +pcfg-pull-none-12ma   +pcfg-pull-up-12ma  +pcfg-pull-none-smt  '+pcfg-output-highpcfg-output-low <pcfg-input-high G+pcfg-input Gi2c0i2c0-xfer T +Gi2c1i2c1-xfer T+Ji2c2i2c2-xfer T+Ki2c3i2c3-xfer T  +Ptsadctsadc-otp-pin T+ctsadc-otp-out T+duart0uart0-xfer T  +'uart0-cts T uart0-rts T uart1uart1-xfer T+;uart1-cts T+<uart1-rts T+=uart2-m0uart2m0-xfer T+>uart2-m1uart2m1-xfer T uart3-m0uart3m0-xfer Tuart3m0-cts Tuart3m0-rts Tuart3-m1uart3m1-xfer T+?uart3m1-cts T +@uart3m1-rts T +Auart4uart4-xfer T+Buart4-cts T+Cuart4-rts T+Duart5uart5-xfer T+Euart5-cts Tuart5-rts Tspi0spi0-clk T+Qspi0-csn T+Rspi0-miso T +Sspi0-mosi T +Tspi0-clk-hs Tspi0-miso-hs T spi0-mosi-hs T spi1spi1-clk T+Uspi1-csn0 T spi1-csn1 T spi1-miso T+Xspi1-mosi T +Yspi1-clk-hs Tspi1-miso-hs Tspi1-mosi-hs T spi1-csn0-gpio-pin T +Vspi1-csn1-gpio-pin T +Wpdmpdm-clk0m0 Tpdm-clk0m1 Tpdm-clk1 Tpdm-sdi0m0 Tpdm-sdi0m1 Tpdm-sdi1 Tpdm-sdi2 Tpdm-sdi3 Tpdm-clk0m0-sleep Tpdm-clk0m1-sleep Tpdm-clk1-sleep Tpdm-sdi0m0-sleep Tpdm-sdi0m1-sleep Tpdm-sdi1-sleep Tpdm-sdi2-sleep Tpdm-sdi3-sleep Ti2s0i2s0-8ch-mclk Ti2s0-8ch-sclktx T+)i2s0-8ch-sclkrx T i2s0-8ch-lrcktx T+*i2s0-8ch-lrckrx T i2s0-8ch-sdo0 T++i2s0-8ch-sdo1 Ti2s0-8ch-sdo2 Ti2s0-8ch-sdo3 Ti2s0-8ch-sdi0 T+,i2s0-8ch-sdi1 T i2s0-8ch-sdi2 T i2s0-8ch-sdi3 Ti2s1i2s1-2ch-mclk Ti2s1-2ch-sclk T+-i2s1-2ch-lrck T+.i2s1-2ch-sdi T+/i2s1-2ch-sdo T+0i2s2i2s2-2ch-mclk Ti2s2-2ch-sclk T+1i2s2-2ch-lrck T+2i2s2-2ch-sdi T+3i2s2-2ch-sdo T+4sdmmcsdmmc-clk T+msdmmc-cmd T+nsdmmc-det T+osdmmc-bus1 Tsdmmc-bus4@ T+psdiosdio-clk T+ssdio-cmd T+rsdio-bus4@ T+qemmcemmc-clk T +temmc-cmd T +uemmc-rstnout T emmc-bus1 Temmc-bus4@ Temmc-bus8 T+vemmc-reset T +flashflash-cs0 T+~flash-rdy T +flash-dqs T +flash-ale T +{flash-cle T +}flash-wrn T +flash-csl Tflash-rdn T+flash-bus8 T+|sfcsfc-bus4@ T+zsfc-bus2 Tsfc-cs0 T+ysfc-clk T +xlcdclcdc-rgb-dclk-pin Tlcdc-rgb-m0-hsync-pin Tlcdc-rgb-m0-vsync-pin Tlcdc-rgb-m0-den-pin Tlcdc-rgb888-m0-data-pins T     lcdc-rgb666-m0-data-pins T     lcdc-rgb565-m0-data-pins T     lcdc-rgb888-m1-data-pins T   lcdc-rgb666-m1-data-pins T   lcdc-rgb565-m1-data-pins T   pwm0pwm0-pin T+[pwm1pwm1-pin T+\pwm2pwm2-pin T +]pwm3pwm3-pin T+^pwm4pwm4-pin T+_pwm5pwm5-pin T+`pwm6pwm6-pin T+apwm7pwm7-pin T+bgmacrmii-pins T +kmac-refclk-12ma T +lmac-refclk T cif-m0cif-clkout-m0 T dvp-d2d9-m0 T   dvp-d0d1-m0 T d10-d11-m0 Tcif-m1cif-clkout-m1 Tdvp-d2d9-m1 T  dvp-d0d1-m1 Td10-d11-m1 Tispisp-prelight Tledsmodule-led-pin T+sd-card-led-pin T +pmicpmic-int T+Hhaikouhaikou-keys-pinP T+emmc-pwrseqmmc-pwrseq-emmcVHdefault b +wleds gpio-ledsHdefaultVokayled-0 m nheartbeat wheartbeat led-1 mZ  wmmc2 nsd vccsys-regulatorregulator-fixed vcc5v0_sysVjLK@)LK@+Ichosen serial0:115200n8gpio-keys gpio-keysVHdefaultbutton-batlow-n BATLOW#  mZbutton-slp-btn-n SLP_BTN#  mbutton-wake-n WAKE#  mswitch-lid-btn-n LID_BTN#   mZi2s0-soundsimple-audio-card i2s Haikou,I2S-codec   *simple-audio-card,codec L V+simple-audio-card,cpu Lsgtl5000-oscillator fixed-clock%w+Ldc-12v-regulatorregulator-fixeddc_12vVj)+vcc3v3-baseboard-regulatorregulator-fixedvcc3v3_baseboardVj2Z)2Z i+Nvcc5v0-baseboard-regulatorregulator-fixedvcc5v0_baseboardVjLK@)LK@ i+vdda-codec-regulatorregulator-fixed vdda_codecj2Z)2Z i+Mvddd-codec-regulatorregulator-fixed vddd_codecjj)j i+O compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0mmc1rtc0rtc1mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qosoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cellsrockchip,trcm-sync-tx-only#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio-oscgpi-supplyphysphy-namesrockchip,outputremote-endpointrts-gpiosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendVDDA-supplyVDDIO-supplyVDDD-supplypagesizevcc-supplynum-cscs-gpios#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usphy-supplyclock_in_outbus-widthfifo-depthmax-frequencyvqmmc-supplysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50cap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplymmc-hs200-1_8vmmc-pwrseqnon-removableiommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsoutput-highline-namegpio-hoginputbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-lowinput-enablerockchip,pinsreset-gpiosfunctionlinux,default-triggercolorstdout-pathlabellinux,codelinux,input-typesimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssimple-audio-card,frame-mastersimple-audio-card,bitclock-mastersound-daisystem-clock-fixedvin-supply